1. INTRODUCTION
Nanotechnology has affected nearly every field of Engineering and Science but most of the innovation and funding (private) in Nanotechnology came from Electronics giants, in search for making faster computers. The other fields that worked with nano electronics hand in hand were nano-photonics and nano-instrumentation. Also the marketing and making of nano gadgets started from the computers and mobiles which are the only machines made at nano scale that were available economically in the market at a very early stage. So it is of no doubt that the only area where nanotechnology penetrated deeply is electronics where it had lead to cost advantage and performance attributes especially in transistors and today we have 1 billion transistors in the latest processor. The backbone of nanotechnology in electronics are the results that we have taken from nano physics that is quantum physics and solid state physics because then we talk of things at nano scale these are the two stream of physics that helps us in predicting things. Eventually when we talk of electronics it is all about electrons and how we use them in various gadgets to get the required result. So it is very important to know electrons and how it behaves at nano scale in electronics.
Introduction and Importance Quantum Mechanics A fundamental aspect of quantum mechanics is the particle-wave duality, introduced by De Broglie, according to which any particle can be associated with a matter wave whose wavelength is inversely proportional to the particle's linear momentum. Whenever the size of a physical system becomes comparable to the wavelength of the particles that interact with such a system, the behavior of the particles is best described by the rules of quantum mechanics. All the information we need about the particle is obtained by solving its Schrodinger equation. The solutions of this equation represent the possible physical states in which the system can be found. But quantum mechanics is not required to describe the movement of objects in the macroscopic world. The wavelength associated with a macroscopic object is in fact much smaller than the object's size, and therefore the trajectory of such an object can be excellently derived using the principles of classical mechanics. Things change, for instance, in the case of electrons orbiting around a nucleus, since their associated wavelength is of the same order of magnitude as the electron-nucleus distance. We can use the concept of particle-wave duality to give a simple explanation of the behavior of carriers in a semiconductor nanocrystal. In a bulk inorganic semiconductor, conduction band electrons (and valence band holes) are free to move throughout the crystal, and their motion can be described satisfactorily by a linear combination of plane waves whose wavelength is generally of the order of nano-meters. This means that, whenever the size of a semiconductor solid becomes comparable to these wavelengths, a free carrier confined in this structure will behave as a particle in a potential box. The solutions of the Schrodinger equation in such case are standing waves confined in the potential well, and the energies associated with two distinct wave functions are, in general, different and discontinuous. This means that the particle energies cannot take on any arbitrary value, and the system exhibits a discrete energy level spectrum. Transitions between any two levels are seen as discrete peaks in the optical spectra, for instance. The system is then also referred to as ''quantum confined''. The main point here is that in order to rationalize (or predict) the physical properties of nanoscale materials, such as their electrical and thermal conductivity or their absorption and emission spectra, we need first to determine their energy level structure.
2. THEORY OF NANO-ELECTRONICS
2.1 PRESENT STATE OF NANO-ELECTRONICS. Moore's law states that the number transistor on an integrated chip for a component doubles every two years. How ever this law does not holds perfectly true for RAM (Random Access memory). This does not mean that the number of transistor on a chip increases but about the density of transistors at which the cost per transistor is the lowest.Currently processors are fabricated at 90nm and 65nm that are being introduced by Intel. The 90 nanometer (90 nm) process refers to the level of semiconductor process or fabrication technology that wasachieved in the 2002-2003 period, by most leading semiconductor companies, like Intel, Texas Instruments, IBM etc. However it is not true for RAM and hard disk. New materials seeing possible use in nano-electronics and will probably keep this law on track. The future is seen as molecular electronics but there is lots of work still to be done to make that possible.
2.2 SILICON NANOTECHNOLOGY
2.2.1 CMOS Nanotechnology
For the past several decades, miniaturization in silicon integrated circuits has pro- gressed steadily with an exponential scale described by Moore's Law. This incredible progress has generally meant that critical dimensions are reduced by a factor of two every three years, while chip density increases by a factor of four over this period. However, modern chip manufacturers have been accelerating this pace recently, and currently chips are being made with gate lengths in the 45 to 65 nm range. More scaling is expected, however, and 15-nm gate lengths are scheduled for production before the end of this decade.
In MOSFET there is electric field between the gate and the semiconductor is such that an inverted carrier population is created and forms a conducting channel. This channel extends between the source and drain regions, and the transport through this channel is modulated by the gate potential. As the channel length has gotten smaller, there has been considerable effort to incorporate a variety of new effects into the simple (as well as the more complex) models. These include short-channel effects, narrow width effects, degradation of the mobility due to surface scattering, hot carrier effects, and velocity overshoot. Ballistic transport in the MOSFET (discussed in later part) Thermodynamics is just as significant in limiting scaling as the preceding effects. The first way it limits scaling is in its control of the subthreshold behavior of MOSFETs. The subthreshold current of a MOSFET originates in the high-energy tail of the statistical distribution of carriers in its source region. The carriers in the source are governed by Fermi-Dirac statistics, and so the tail of the distribution is essentially Boltzmann.
There two major scattering regions - the barrier between the channel and the source and within the channel.
There also exists a phenomenon Granularity is the failure of thermodynamic averaging in small devices. Quantum behavior in the device, there are two effects and Effective Carrier Wave Packet . These effects also include tunneling through the gate insulator, tunneling through the band gap, quantum confinement issues, interface scattering, discrete atomistic effects in the doping and at interfaces, and thermal problems associated with very high power densities.
Ballistic Properties:-
It is the phenomenon where the the contribution in electrical resistivity due to scattering by the atoms, molecules or impurities in the medium itself, is negligible or absent meaning the electron can move without hindrances. There is no loss of kinetic energy due to collision of hitting of electrons with atom of metal thereby electrons move in a mean free path where it can move freely.
Quantum mechanical scaling limitations include both confinement effects and tun- neling effects. Confinement effects occur when electron or hole wave functions are squeezed into narrow spaces between barriers. In FETs this primarily happens in the channel, where the charges are squeezed between the gate insulator on one side and the built-in field of the body on the other side. Quantum confinement in this approximately triangular well raises the ground state energy of the electrons or holes, which increases the threshold voltage, and shifts the mean position of the carriers a little farther from the Si-SiO2 interface. Quantum mechanical tunneling is generally more detrimental to scaling than the Confinement effects. When electrons or holes tunnel through the barriers of the FET, it causes leakage current. As scaling continues, this ultimately causes unacceptable increases in power dissipation. The leakage may also cause some types of dynamic logic circuits to lose their logic state, but the former problem usually seems to arise first.
There are primarily two forms of tunneling leakage: tunneling current through the gate insulator, and tunneling current through the drain-to-body junction. The atomistic effects that cause limitations to scaling are those in which the discreteness of matter gives rise to large statistical variations in small devices. These statistical variations occur because the atoms or molecules tend to display Poisson statistics in their number or position, and the Poisson distribution for small numbers can become very wide.
2.2.2 Memory
As the semiconductor device feature size enters the sub-50-nm range, two new effects come into play. One is the quantum effect, which is rooted in the wave nature of the charge carriers, and gives rise to non classical transport effects such as resonant tunneling and quantum interference. The other is related to the quantized nature of the electronic charge, often manifested in the so-called single-electron effect: Charging each electron to a small confined region requires a certain amount of energy in order to overcome the Coulomb repulsion; if this charging energy is greater than the thermal energy, kb*T (kb Boltzman constant, T temperature), a single electron added to the region could have a significant effect on other electrons entering the confined region.
To increase the storage density of semiconductor memories, the size of each memory cell must be reduced. A smaller memory cell also leads to higher speed and lower power consumption. This is the incentive for studying the nanoscale semiconductor memory. One of the general schemes for semiconductor data storage is by storing charges on a capacitor. The charged state and the uncharged state can be used to represent binary information 1 and 0, respectively. Usually charges are transferred to the capacitor through a resistive. The motivation for this work is to investigate the ultimate limit of a floating gate MOS memory. In a conventional floating gate memory, there are typically on the order of 10 to power 4 electrons stored on the floating gate to represent one bit of information. The ultimate limit in scaling down the floating gate memory is to use only one electron for the same purpose, hence the name "single-electron MOS memory" (SEMM). The advantage of such a memory is that not only can it be very small, but also it can provide some unique characteristics that are not available in the conventional device, such characteristics as quantized threshold voltage shift and quantized charging voltage.
To make single-electron memory practical, both thermal fluctuation and quantum fluctuations of the stored charge have to be minimized. In order to reduce the variation in the device structure, we would like to build a single-electron memory device in crystalline silicon that has well-controlled dimensions. We defined the transistor channel and the floating gate by using lithography. Finally, the single-electron memory potentially has a number of advantages over conventional memories: (1) the quantized characteristics of the device make it immune to the noise from the environment-unless the noise level reaches a certain threshold, it will not affect the memory state. The immunity to noise is especially important for the future terabits integration, simply because of the sheer large number of devices present on a single small chip area. (2) the inherent quantized nature of the SEMM makes it possible to easily implement multilevel logic storage in a single memory cell; (3) the device can operate at a higher speed due to the use of only one or few electrons during writing and erasing; (4) for the same reason, the device can also have ultralow power consumption.
2.3 NANO TUBES, CNT ELECTRONICS.
Single-walled carbon nanotubes (SWNTs), which are graphite cylinders made of a hexagonal carbon-atom lattice, have drawn a great deal of interests due to their Fundamental research importance and tremendous potential technical applications . For Example, they might play an important role in future molecular electronic devices, such as room-temperature single electron and field-effect transistors , and rectifiers . A SWNT can be either a semiconductor or a metal, depending on its helicity and diameter. The electronic properties of the SWNT have been the subject of an increasing number of experimental and theoretical studies since 1995. And it is expected that very soon SWNT will see it's application in Nano electronics. SWNT is going to see it's application in transistors where it can reduce the gate length and also reduce leakage current. SWNTs have very low electrical resistance. Resistance occurs when an electron get deflected away from its path, when it is traveling through a material. In a 3-D conductor, electrons have plenty of opportunity to scatter, since they can do so at any angle. All these scatterings will give rise to electrical resistance. The situation is different in 1D. In a truly 1D conductor, however, electrons can only travel forward or backward. Only backscattering will lead to electrical resistance. But backscattering in nanotubes is impeded by the special symmetry of graphite and carbon nanotubes, and is therefore less likely to happen. Because of this, electrons can travel in nanotubes for long distances without being scattered, and this type of ballistic transport has been observed experimentally
2.4 NANO WIRES
A nanowire is a wire of dimensions of the order of a nanometer. They are also called quantum wires because their properties are governed by quantum mechanics. They can be used to link or connect tiny component is nanocircuits. They are referred as 1 dimensional materials (because their length to width ratio is very high). The electrons here are quantum confined and occupy different energy levels than those of bulk material. They will see their application in electronics, opto-electronics and Micro Electro mechanical systems. They will be seeing possible applations in future molecular electronic devices, as resonant tunneling diodes, single-electron transistors, and field effect structures and also in making logic gates.
2.5 QUANTUM DOT
It is the semiconductor nanostructure which exhibits the phenomenon of confining motions of electrons of conduction, valence or excitons in all three spatial directions. They have superior quantum and optical properties and are being researched for diode laser, amplifier, sensors, etc. They are also seeing application in Light Emitting Diodes(Quantum Dot Single Electron Device). The ability to control electron charging of a capacitive node by individual electron makes there devices suitable for memory application. A quantum well is a potential well that confines particles, which were originally free to move in three dimensions, to two dimensions, forcing them to occupy a planar region
3. MANUFACTURING CHALLENGES Nanofabrication is being developed to construct devices such as resonant tunneling diodes and transistors and single electron transistors and carbon nanotube transistors. The most common type of transistor being developed for use at the nanoscale is the field effect transistor. Economics issues are constraining nano-electronics to hit market. Two ways of manufacturing nano materials are:-
1. Bottom up self assembly (wet chemistry) In this type of fabrication we start from atoms or molecules to get to the desired material.
2. Top down self assembly (Lithography and derivatives) In this type of fabrication the bulk material is broken down into smaller pieces. Thought we have knowledge about many new materials and their physics at nanoscale but to get the technology economically available (cost effective) and to get the state of art levels of manufacturing nanomaterials is still under development.
4. ABBREVIATION:-
IBM - International Business Machine
CMOS - Complimentary metal oxide semiconductor
CNT - Carbon nanotube
SWNT - Single Walled Nano Tube (carbon nanotube in most cases)
MOSFET - Metal-oxide-semiconductor field-effect transistor
The advances in ultra-large-scale integration (ULSI) technology mainly have been based on downscaling of the minimum feature size of complementary metal-oxide semiconductor (CMOS) transistors. The limit of scaling is approaching and there are unsolved problems such as the number of electrons in the device’s active region. If this number is reduced to less than 10 electrons (or holes), quantum fluctuation errors will occur and the gate insulator thickness will become too small to block quantum mechanical tunneling, which may result in unacceptably large leakage currents. On the other hand, the recent evolution of nanotechnology may provide opportunities for novel devices, such as single-electron devices, carbon nanotubes, Si nanowires, and new materials, which may solve these problems. Utilization of quantum effects and ballistic transport characteristics also may provide novel func- tions for silicon-based devices. Among various candidate materials for nanometer scale devices, silicon nanodevices are particularly promising because of the existing silicon process infrastructure in semiconductor industries, the compatibility to CMOS circuits, and a nearly perfect interface between the natural oxide and silicon.
For the past several decades, miniaturization in silicon integrated circuits has pro1 gressed steadily with an exponential scale described by Moore’s Law. This incredible progress has generally meant that critical dimensions are reduced by a factor of two every three years, while chip density increases by a factor of four over this period. However, modern chip manufacturers have been accelerating this pace recently, and currently chips are being made with gate lengths in the 45 to 65 nm range. More scaling is expected, however, and 15-nm gate lengths are scheduled for production before the end of this decade. Such devices have been demonstrated by Intel and AMD, and IBM has recently shown a 6-nm gate length p-channel FET. While the creation of these very small transistors is remarkable enough, the fact that they seem to operate in a quite normal fashion is perhaps even more remarkable.